How sample and hold works: a capacitor remembers

What you're hearing

A capacitor remembers a voltage, and a JFET decides when. Charge a capacitor and then let go of it, and the charge has nowhere to go, so its voltage stays. That's the "hold": here it's C1, 100 nF. The "sample" is a switch that joins C1 to the input for a moment, so it takes on the input's voltage. The switch is J1, a J111 JFET. It conducts between its two channel pins while its gate is near their voltage, and turns off once the gate is about 5 V below them. Fully on, it's about 46 Ω in SynthMaker's model, so C1 charges with a time constant of 46 Ω × 100 nF = 4.6 µs.

The clock turns the switch on for about 50 µs. The gate rests at −10 V, from V1 through Rp, 68 kΩ: off. The clock is a square wave, which arrives as −5 V and +5 V, through Cp, 1 nF, which passes only its edges. A rising edge is 10 V, which lifts the gate from −10 V to 0 V: on. Rp then pulls it back with a time constant of 68 kΩ × 1 nF = 68 µs, past −5 V after 68 µs × ln 2 = 47 µs, and the switch is off. In that window C1 gets about six time constants of charging, so it lands within 1% of the input for a voltage near 0 V. The gate has to fall fast: with Rp at 220 kΩ, the switch still conducts a little on the noise's lowest dips as it turns off, and the steps drift low, a mean of −0.15 V over 15 s of noise (with 68 kΩ, +0.02 V). Without Cp, a square wave would hold the switch on for half of every cycle, so the output would follow, then hold, then follow: a track and hold.

Fed noise, it makes random steps, one per tick. Noise is a voltage that never settles, far too fast to use as a control. The sample and hold catches it at one instant on each tick and keeps that voltage, so the clock sets the step rate exactly: a new level every 200 ms at 5 Hz, every 62.5 ms at 16 Hz. Here the steps move a filter's cutoff, from 124 Hz to 3.96 kHz across steps from −1 V to +1 V. Feed it something slow and it draws a staircase. In "A slow triangle in", the triangle rises from −1 V to +1 V in 1 s, 2 V per second, and the clock is 8 Hz, so each tick catches it 0.25 V further on: eight steps up, eight down.

Droop: whatever reads the capacitor drains it. Press "Load on the capacitor". The 1 MΩ load now hangs on C1 itself, and every bit of current it takes comes out of C1's charge. The voltage falls as V × e^(−t/RC), with RC = 1 MΩ × 100 nF, about 0.1 s. A held 1 V starts falling at 10 mV per ms, and by the next tick at 5 Hz only 13% of it is left. Each step sags back towards 0 V before the next arrives, so the filter keeps closing back to the middle.

Two buffers: one stops the droop, one fills the capacitor in time. In the other buttons, the load hangs from U2, an op-amp buffer. Its input takes no current, so it copies C1's voltage without taking anything from it, and gives the load all the current it wants (see the op-amp's two rules). All that drains C1 now is Rl, 100 MΩ, which stands for the small leaks of a real capacitor and a real op-amp's input. That's a time constant of 10 s: 0.1 mV per ms from 1 V, about 100 times slower, and 98% is still there after 200 ms. U1 does the opposite job on the way in. C1 has only about 50 µs to charge, and a weak source can't push enough current in that moment: through 4.7 kΩ, the time constant is 4.7 kΩ × 100 nF = 0.47 ms, ten times the window, so C1 gets only about 9% of the way on each tick. U1 supplies the current, so C1 reaches the input's voltage at once.

What the model covers, and what it leaves out. The J111 is a standard JFET model with typical values: its data sheet gives at most 30 Ω when on, where the model gives 46 Ω, which makes no difference at these capacitor sizes. It has no capacitance inside, so a real gate's edge would kick a small jump onto the held voltage, and this one doesn't. The switch is on for only about two samples at 48 kHz, but C1 charges much faster than that, so each tick still lands within about 1% of the input, and the steps stay within the noise's own ±1 V.

Try this

• Press "Load on the capacitor: it droops", then "Clock 5 Hz, buffered". The filter's jumps fade back to the middle between ticks, then stay put. The parts are the same: only the load has moved.
• Press "Clock 16 Hz: it bubbles", and turn input from 1 V down to 0.1 V. The steps shrink to a tenth, so the cutoff moves only a quarter of an octave either way.
• Open it in SynthMaker to change the parts. Replace U1 in b b opamp with Rs in b 4.7k, a weak source with no input buffer: each tick fills C1 only about 9% of the way, so the steps come out small and all near 0 V. Or set the clock's LFO to 1 Hz, and the filter wanders instead of bubbling.

The parts list

circuit SampleHold  oversample 1x  setting input: 1 V, from 0.1 V to 2 V  in gate  V1 rest gnd -10V  U1 in b b opamp  Cp gate g 1n  Rp rest g 68k  J1 b g hold J111  C1 hold gnd 100n  Rl hold gnd 100M  U2 hold out out opamp  Rload out gnd 1Mend

in gate is the clock's way in: wire a square LFO into it. A wire's 1 is 5 V there, so the LFO swings from −5 V to +5 V. J1 is written drain, gate, source. Rload stands for whatever reads the steps; for the droop, change it to Rload hold gnd 1M. It's a slow voltage, so it runs at 1×, with no oversampling.

How we checked it

Checked against ngspice, a standard circuit simulator: the hold's droop matches it within 7 µV. What it grabs is the input at the nearest sample of the 48 kHz grid, and the step it holds is within 1% of what it grabbed. Measured in SynthMaker: buffered, the steps droop 0.1 mV per ms per volt (98% left after 200 ms); with the load on the capacitor, 10 mV per ms per volt (13% left).

Build it step by step

• The lesson: Random voltages from noise (opens in a new tab). Ned builds this sample and hold a part at a time: a capacitor remembering a pulse, the JFET switch, the clock's edges, the sag and the two buffers. Then he plays it into a filter and with drums.
• The video: Turn noise into a burbling synth filter: a sample and hold, built from parts. It loads only when tapped.
• The manual: Sample and hold.

Turn noise into a burbling synth filter: a sample and hold, built from parts

Next and previous

• Previous: How a slew limiter works: slew and portamento (planned)
• Next: How a white noise generator works (planned)

All circuits

Further reading

• What a sample and hold is, and its droop: Wikipedia: Sample and hold.
• Sample and hold on a synth, and how its stepped voltages lead to digital sampling: G. Reid, "From Sample & Hold To Sample-rate Converters (1)", Synth Secrets, Sound On Sound. Article
• The JFET, and how its gate turns its channel off: Wikipedia: JFET.
• The J111 data sheet: its pinch-off voltage, on-resistance and gate limits. PDF
• How a capacitor charges and discharges through a resistor: Wikipedia: RC time constant.
• Why a buffer stops loading: Wikipedia: Buffer amplifier.
• How SynthMaker simulates a circuit: M. Holters and U. Zölzer, "A Generalized Method for the Derivation of Non-Linear State-Space Models from Circuit Schematics", EUSIPCO 2015. PDF