3th order interpolated delay updated

sambean · 5 Jun 2006

Hey Luisi,

Thanks for sharing! I think there may be a slight flaw in the implementation though.. If you hook it up to an analyser with 10 or so samples analysed, feed an impulse for input, and control the delay with a knob in the range 0-10, you'll see that the impulse does not move 'smoothly' from one sample to the next..

I think this section should be:

temp1 = index - intdelay; temp2 = temp1 + 1; temp3 = temp1 - 1; temp4 = temp1 - 2;

Also setting delay to zero, you get no output, you should write to the table first, then read to solve this...

If you're interested here's my own fractional delay using allpass filters:

stage(1) { mem[index]=in;

intdelay = delay - 0.499999; intdelay = rndint(intdelay); frac = delay - intdelay;

temp1 = index - intdelay; temp2 = temp1 - 1;

temp1 = temp1 + (temp1 < 0)&MAXDELAY; temp1 = mem[temp1];

temp2 = temp2 + (temp2 < 0)&MAXDELAY; temp2 = mem[temp2];

frac = (1 - frac)/(1 + frac); out = temp2 + frac * (temp1 - out1); out1 = out;

index=index+1; index=(index<MAXDELAY)&index; }

Cheers

Sam

luisi · 5 Jun 2006

I think this section should be:

temp1 = index - intdelay; temp2 = temp1 + 1; temp3 = temp1 - 1; temp4 = temp1 - 2;

I didn't try that but I think that you could be right since in my C code I scan the buffer in reversed mode where in the SM code I don't,

thanks for pointing that!

thanks also for your delay with allpass filters, I've found it in the examples, <wink>

about the delay to zero, if you write to the table first your delay is delay lenght + 1 sample always, wrong?

ROMplERbuDE · 24 Jun 2006

Hy, //del

//del

I has made an (4Point) example that has fixup that .... It is not the best but it works for delay modulation (flanger with < 10 & > 600 smpls).

[old link]

infuzion · 25 Jun 2006

neat little flange ROMplERbuDE, thanks!

ROMplERbuDE · 25 Jun 2006

Yeah thank you infuzion for Feedback...

luisi · 29 Jun 2006

Hi ROMplERbuDE,

many thank for for your nice 4P delay!

may you please tell me more about the usage of stage(2) and stage (4), why you chose that?

ROMplERbuDE · 30 Jun 2006

Hy luisi, No probs i will share more ideas. stage(4) ???? I never heard before..... stage(2,3) delays a signal by one samp I think. The once info that I have seen is @: [old link]

luisi · 30 Jun 2006

ROMplERbuDE wrote: Hy luisi, No probs i will share more ideas. stage(4) ???? I never heard before..... stage(2,3) delays a signal by one samp I think. The once info that I have seen is @: [old link]

yes 2 and 3, but still I don't get why you used them, <grin>

ROMplERbuDE · 30 Jun 2006

I have tried to reduce clicks by less delay times <4smpls... 🙂

luisi · 1 Jul 2006

ROMplERbuDE wrote: I have tried to reduce clicks by less delay times <4smpls... 🙂

ah, thanks, <grin>

sambean · 1 Jul 2006

Stages 1,2 and 3 all get calculated in the same sample period but in that order. So calculation is all stage 1 then all stage 2 then all stage 3, if you get my drift..

The reason for the different stages is to make sure that schematics with delays and feedback are calculated correctly.. I'm not sure of the exact details but I think it should be as follows:

stage 1 calculate all schematic 'maths' stage 2 calculate all delay outputs stage 3 calculate all delay inputs

When you have a feedback path, this will stop ambiguities in the order of the calculation.

Here's a link to a topic which illustrates why there are stages 2&3 with an explanation by Jorge..

[old link]

Excuse my ignorance half way through the discussion 😊

Sam

ROMplERbuDE · 1 Jul 2006

Hy Sam, thanks for the info.

Did you mean for a smpl. feedback that first the signal goes in stage(3) then calculate in (1) then go out in (2)?

jorge · 1 Jul 2006

Stages are just a way of grouping compiled code. For example if you have 2 code components let's say CCA and CCB and you use stages 1 2 and 3 on both, the resulting compiled code will be the following:

CCA stage 1 CCB stage 1 CCA stage 2 CCB stage 2 CCA stage 3 CCB stage 3

In most cases only stage 1 is needed. When you're using delays to create digital filters, in order to avoid different results depending on the order that you insert the components, stage 1 can be used to do all the calculations and stages 2 and 3 to move data in and out of the internal memory of the delays. That's the only reason I've needed stage 2 and 3 so far and the reason they were implemented although there might be other uses for them.

ROMplERbuDE · 3 Jul 2006

Ok, Thank you jorge. I will understand it now!