fastest code ABS()?

doug4350 · 31 Mar 2006

(1) If it's optimized correctly, bool-$4it 🙂 are processor opcodes, which can be bool-dozed at the cpu register level. Whereas max(...) is a function which requires more overhead pushing the code component registers on the stack so they don't get stepped on in max() and popping them off coming back. (I'm assuming the 'C' calling convention is used of course).

(2) Makes sense 2 me. I'm not sure what the func constructs do?.?. Anyone care to clarify???

Aloha, Doug

infuzion · 31 Mar 2006

doug4350 wrote: (1) ...Whereas max(...) is a function which requires more overhead pushing the code component registers on the stack so they don't get stepped on in max() and popping them off coming back.

Seems to be, but if you connect a Text to the Code's output, you'll see the assembly for the mask-version: streamin in; streamout abs; float absmask=0.0000000000; float F339999995214436420000000000000000000000P0000000000=339999995214436420000000000000000000000.0000000000; float F0P9999989867=0.9999989867; float F0P1000000015=0.1000000015; stage0; movaps xmm0,F339999995214436420000000000000000000000P0000000000; orps xmm0,F0P9999989867; movaps xmm1,xmm0; orps xmm1,F0P1000000015; //Assignment> sLeft=xmm1 movaps absmask,xmm1; stage1; stage1; movaps xmm0,in; andps xmm0,absmask; //Assignment> sLeft=xmm0 movaps abs,xmm0; stage1; Seems to be quite a lot of steps setting up absmask? & the Max version: streamin in; streamout abs; float F0P0000000000=0.0000000000; movaps xmm0,F0P0000000000; subps xmm0,in; movaps xmm1,xmm0; maxps xmm1,xmm0; maxps xmm1,in; //Assignment> sLeft=xmm1 movaps abs,xmm1; I can see how 2 maxps-s will slow things up...but is it significant?

doug4350 · 31 Mar 2006

Good point Infuzion... I don't know 'nuff about the code component to be that clever yet 🙂 . So they have opcodes for the max() stuff these days ... cool. Kind of like when I believe it was the 486 introduced the strcmp() replacement opcode.

I left X86 assembly (coding anyways) on the shelf waayyyyy back in the 286 days. I haven't dabbled much with the code component, but just rambling from past experience. What you need to do to answer the question is look at the clock cycle cost of the maxps opcode. My gut tells me it's more than a logical and/or opcodes. Way back on the 8086, the and/or opcodes took only 4 cycles. I'm sure nowadays with prefetch/readahead/predictor queueing, it could be less. There's also the issue of byte alignment. I believe since the pentium family of recent, being 64 bits would require 8 byte byte alignment (8 bytes * 8 bits/byte == 64 bits) for maximum thrust, that if the data isn't aligned, there's cpu cost to do it transparently. As a side note, I think there's too much hype, or maybe misleading on the megabyte ram thing. The reason is if you have a 64 bit machine with 1 GB of ram, effectively, you sort of only have 128 MB, or you trade the alignment cost. I'm rambling on that because floats are only 4 bytes. When it comes down to tooth & nail, ya gotta look at the ram during execution. Isn't this fun 🙂 .

'K den. It's almost 10:30 p.m. here and I need to get some ivory time in b4 lights out.

Aloha, Doug

doug4350 · 31 Mar 2006

Good point Infuzion... I don't know 'nuff about the code component to be that clever yet 🙂 . So they have opcodes for the max() stuff these days ... cool. Kind of like when I believe it was the 486 introduced the strcmp() replacement opcode. One of these days I should take a peek at the sse opcodes...

I left X86 assembly (coding anyways) on the shelf waayyyyy back in the 286 days. I haven't dabbled much with the code component, but just rambling from past experience. What you need to do to answer the question is look at the clock cycle cost of the maxps opcode. My gut tells me it's more than a logical and/or opcodes. Way back on the 8086, the and/or opcodes took only 4 cycles. I'm sure nowadays with prefetch/readahead/predictor queueing, it could be less. There's also the issue of byte alignment. I believe since the pentium family of recent, being 64 bits would require 8 byte byte alignment (8 bytes * 8 bits/byte == 64 bits) for maximum thrust, that if the data isn't aligned, there's cpu cost to do it transparently. As a side note, I think there's too much hype, or maybe misleading on the megabyte ram thing. The reason is if you have a 64 bit machine with 1 GB of ram, effectively, you sort of only have 128 MB, or you trade the alignment cost. I'm rambling on that because floats are only 4 bytes. When it comes down to tooth & nail, ya gotta look at the ram during execution. Isn't this fun 🙂 .

'K den. It's almost 10:30 p.m. here and I need to get some ivory time in b4 lights out.

Aloha, Doug